5 ms·

These are all work-arounds: the permanent fix is to expose the processor’s carry and zero flags in C.

by Annatar 8y ago

saagarjha 8y ago
Not every processor has these flags.
- Annatar 8y ago
  Processors had these en masse (6502, Z80, MC68000) since the ‘70’s of the past century. Without those, it’s extremely difficult to implement basic arithmetic with numbers larger than what the processor’s registers support. Which contemporary processors don’t have the C and Z status bits? Post scriptum, since “Hacker News” is of the opinion that I’m posting too fast: MIPS does have a status register, and this register does have an overflow bit: https://www.doc.ic.ac.uk/lab/secondyear/spim/node10.html https://www.doc.ic.ac.uk/lab/secondyear/spim/node10.html
  - saagarjha 8y ago
    MIPS? ------------------ Addendum addressing your updates: > MIPS does have a status register, and this register does have an overflow bit: Yes, it does, but it doesn't function as a simple carry or zero bitfield. In MIPS, there are two instructions for performing addition: add and addu. add generates a trap which you can respond to in an exception handler (which is where you check for this exception code)–as opposed to addu, which overflows silently. Most programs explicitly looking to check for overflow just use addu followed by a sltu (set less than, unsigned).
    - Annatar 8y ago
      “u” in “addu” means unsigned, so if I’m using it, I understand what the implication is.
      - saagarjha 8y ago
        What implication are you talking about?
        Annatar 8y ago
        That there is no bit used for the sign, and so I know when the registers will overflow. A lot of the assembler code I wrote exploits this very fact, since when used cleverly it’s a performance optimization.
  - AstralStorm 8y ago
    Unfortunately, the bit has overloaded meaning. Plus you're still injecting expensive branches which the branch slot is unlikely to fix.
    - Annatar 8y ago
      You’ll never feel that penalty if you’re writing the assembler code by hand, not even on the oldest, slowest MIPS processor, and if you’re using a compiler, the compiler intrinsic has to do the same thing.
- snaky 8y ago
  And not without a reason. https://yarchive.net/comp/carry_bit.html https://yarchive.net/comp/carry_bit.html
  - Annatar 8y ago
    Mashey has a good argument, however I think that the sr overload could be solved with one sr per pipeline. For example, if the CPU is a six pipeline superscalar design, like MIPS R10000 was, implement sr0 to sr5.

These are all work-arounds: the permanent fix is to expose the processor’s carry and zero flags in C.

saagarjha 8y ago

Not every processor has these flags.

Annatar 8y ago
Processors had these en masse (6502, Z80, MC68000) since the ‘70’s of the past century. Without those, it’s extremely difficult to implement basic arithmetic with numbers larger than what the processor’s registers support. Which contemporary processors don’t have the C and Z status bits? Post scriptum, since “Hacker News” is of the opinion that I’m posting too fast: MIPS does have a status register, and this register does have an overflow bit: https://www.doc.ic.ac.uk/lab/secondyear/spim/node10.html https://www.doc.ic.ac.uk/lab/secondyear/spim/node10.html
- saagarjha 8y ago
  MIPS? ------------------ Addendum addressing your updates: > MIPS does have a status register, and this register does have an overflow bit: Yes, it does, but it doesn't function as a simple carry or zero bitfield. In MIPS, there are two instructions for performing addition: add and addu. add generates a trap which you can respond to in an exception handler (which is where you check for this exception code)–as opposed to addu, which overflows silently. Most programs explicitly looking to check for overflow just use addu followed by a sltu (set less than, unsigned).
  - Annatar 8y ago
    “u” in “addu” means unsigned, so if I’m using it, I understand what the implication is.
    - saagarjha 8y ago
      What implication are you talking about?
      - Annatar 8y ago
        That there is no bit used for the sign, and so I know when the registers will overflow. A lot of the assembler code I wrote exploits this very fact, since when used cleverly it’s a performance optimization.
- AstralStorm 8y ago
  Unfortunately, the bit has overloaded meaning. Plus you're still injecting expensive branches which the branch slot is unlikely to fix.
  - Annatar 8y ago
    You’ll never feel that penalty if you’re writing the assembler code by hand, not even on the oldest, slowest MIPS processor, and if you’re using a compiler, the compiler intrinsic has to do the same thing.
snaky 8y ago
And not without a reason. https://yarchive.net/comp/carry_bit.html https://yarchive.net/comp/carry_bit.html
- Annatar 8y ago
  Mashey has a good argument, however I think that the sr overload could be solved with one sr per pipeline. For example, if the CPU is a six pipeline superscalar design, like MIPS R10000 was, implement sr0 to sr5.