3 ms·
> That's _all_ there to support the POWER memory model in some scenarios. Hmm. I’m ignorant of the actual history of the standardization process, but these da
by comex 8y ago
> That's _all_ there to support the POWER memory model in some scenarios.
Hmm. I’m ignorant of the actual history of the standardization process, but these days wouldn’t memory_order_consume benefit ARM systems equally (that is, if compilers were able to actually implement it)? The ARM architecture similarly provides an ordering guarantee for loads whose address depends on previous loads, in what is otherwise a weak memory model.
- BeeOnRope 8y agoYou are probably right: even as I was writing it, I was thinking "Isn't ARM like this too?". A big difference is that recent version of the ARM ISAs have added "acquire" and "release" loads and stores, so they will perform well with those semantics in the future (and ARM chips generally pick up the new ISAs quickly).