3 ms·
I'm still figuring out the microcode. It looks like about 4K x 16 bits. The functional units are arranged with the 64-bit mantissa datapath at the bottom and t
by kens 8y ago
I'm still figuring out the microcode. It looks like about 4K x 16 bits.
The functional units are arranged with the 64-bit mantissa datapath at the bottom and the 16-bit exponent on top. The mantissa functional units have the constants at the left, then the bidirectional shifter, then the ALU, then a 2-bit and 1-bit shifter (for multiplication, etc), then three temporary registers, then register buffers and finally the 8 stack registers. The most significant bit is at the bottom. (Which is backwards to how it is stored with the most significant bit next to the exponent.)
You are correct that above the 8087 logo (to the left and a fair bit to the right) is a shifter. Above is a 0-8 bit shifter and to the right is 0/8/16/.../64 bit shifter. Combined, they allow any bit shift. It's bidirectional (with buffers/drivers on both sides), so you put the bits through one way to shift left and the other way to shift right. (Shifting is a big part of floating point. For instance, to add or subtract, you need to shift the numbers so the decimal points line up. And then you need to shift the results to be normalized.)
As far as layers: The bottom is silicon and doped silicon. The polysilicon for wiring / gates is above. On top is a single layer of metal. The metal and polysilicon are used for routing. Typically metal is mostly vertical and polysilicon is mostly horizontal or vice versa, but there are lots of exceptions. Metal is preferred for long routes (and power) because it has much lower resistance.
- brandmeyer 8y ago> [The shifter is] bidirectional (with buffers/drivers on both sides), so you put the bits through one way to shift left and the other way to shift right. Wait, really? I'm used to seeing mux circuits like the following, which incur a wee bit of gate delay per stage. http://www.vlsitechnology.org/html/cells/vsclib013/mxi2.html http://www.vlsitechnology.org/html/cells/vsclib013/mxi2.html http://www.vlsitechnology.org/html/cells/vsclib013/mxn2.html http://www.vlsitechnology.org/html/cells/vsclib013/mxn2.html