5 ms·

> How arbitrary is arbitrary? ARMv7's Thumb2 format immediates are composed of a 8-bit field shifted by up to 5 bits. So you can form any 32-bit variable, but w

> How arbitrary is arbitrary? ARMv7's Thumb2 format immediates are composed of a 8-bit field shifted by up to 5 bits. So you can form any 32-bit variable, but with limited precision. When it comes to encoding the address of an entry point, every bit of precision you lose (above the first two or three) in the address loses you memory compactness (and adds a certain amount of complexity to compilation and relocation). On the ARM and AArch64 V8 ports they use a constant pool for target addresses, on RISC-V you can probably just use AUIPC to compute the target address in place with no pool address register. You can, of course, do the exact same thing on RISC-V that they do in the ARM ports, but RISC-V has the considerable advantage of four extra bits (totalling 20) in U immediates vs. MIPS (16-bit U immediates), and eight extra bits vs. ARM in some cases (though ARM's immediate encodings are various and sundry, and produce a huge variety of corner cases and microoptimizations which are mostly useless to JITs [in my mostly amateur opinion]; to a lesser extent MIPS also has some interesting features for loading immediates which make up for the shortfalls in AOT code, but are harder [it seems to me, an amateur] to use effectively in a JIT).

brandmeyer 8y ago
AArch64 uses adrp in almost exactly the same way that RISC-V uses auipc to access literal pools. It isn't a strongly distinguishing feature between those architectures. The difference between them is that ADRP computes a 4 kB page-aligned pc-relative address, which complements the 12-bit unsigned address offsets in its base+disp addressing mode to get a uniform +(2 GB -1) to -2GB reach. RISC-V doesn't compute a page-aligned address, in order to partially compensate for the use of signed offsets in its base+disp12 addressing mode. I say partially because RISC-V's PC-relative reach remains asymmetric +(2 GB - 2k - 1) to -(2 GB + 2k), but that probably doesn't matter much as long as you establish an appropriate red zone. ARM distinguishes immediate operands used for data processing and immediate operands used for address generation. The alternative formats I was referring to are mostly just available for the logical operations (although Thumb2 sometimes also uses them for arithmetic). I was thinking that they might make pointer tagging a smidge easier to deal with. *edit: Whoops, 12-bit signed, not 10-bit signed on the asymmetry of the RISC-V reach.
- brucehoult 8y ago
  Your figures seem a little off there. Yes, RISC-V is a little asymmetric, with the AUIPC being able to subtract exactly 2 GB from the PC or add 2GB-4KB to it, and then a jalr/lb/sb can subtract an additional 2 KB or add 2KB-1. But the AArch64 adrp is also asymmetric because the relative reach depends on where in the 4 KB page the original PC is. It's only symmetric if the PC is 4 KB aligned. If you're part way through the page then there is more -ve reach and less +ve reach. A couple of KB fuzziness in what is basically a 32 bit reach in a 64 bit address space is pretty much completely irrelevant in both cases.
  - brandmeyer 8y ago
    ADRP operates on the 4kB page of the pc (by truncation), not the entire pc. RISC-V could have implicitly added 2k in auipc and balanced out the bias. But they didn't.
    - brucehoult 8y ago
      I know how ADRP operates. It's symmetric about the truncated PC. It's not symmetric about the actual PC. As I said in the last post.
      - brandmeyer 8y ago
        I think you are misunderstanding the benefit of having symmetric reach by the page. On AArch64, you can define a 2 GB contiguous slice of address space, built up out of whatever page size you find convenient for your system and plant a relocatable binary into it, up to 2 GB of size. Any instruction anywhere in the last page can reach any address in the first page, and vice versa. In RISC-V, if you try to do the same thing, you'd find that while any instructions in the last page can reach any address in the first page with room to spare. But some instructions in the first page cannot reach portions of the last page. Sure, it doesn't matter most of the time. It isn't ever really an obstacle in practice for the feller writing application code for the platform. But the linker has to be aware of it in the 'medium' code model as a special case for just this particular platform. Somebody had to write that special case to work around the hardware.

brandmeyer 8y ago

AArch64 uses adrp in almost exactly the same way that RISC-V uses auipc to access literal pools. It isn't a strongly distinguishing feature between those architectures. The difference between them is that ADRP computes a 4 kB page-aligned pc-relative address, which complements the 12-bit unsigned address offsets in its base+disp addressing mode to get a uniform +(2 GB -1) to -2GB reach. RISC-V doesn't compute a page-aligned address, in order to partially compensate for the use of signed offsets in its base+disp12 addressing mode. I say partially because RISC-V's PC-relative reach remains asymmetric +(2 GB - 2k - 1) to -(2 GB + 2k), but that probably doesn't matter much as long as you establish an appropriate red zone. ARM distinguishes immediate operands used for data processing and immediate operands used for address generation. The alternative formats I was referring to are mostly just available for the logical operations (although Thumb2 sometimes also uses them for arithmetic). I was thinking that they might make pointer tagging a smidge easier to deal with. *edit: Whoops, 12-bit signed, not 10-bit signed on the asymmetry of the RISC-V reach.

brucehoult 8y ago
Your figures seem a little off there. Yes, RISC-V is a little asymmetric, with the AUIPC being able to subtract exactly 2 GB from the PC or add 2GB-4KB to it, and then a jalr/lb/sb can subtract an additional 2 KB or add 2KB-1. But the AArch64 adrp is also asymmetric because the relative reach depends on where in the 4 KB page the original PC is. It's only symmetric if the PC is 4 KB aligned. If you're part way through the page then there is more -ve reach and less +ve reach. A couple of KB fuzziness in what is basically a 32 bit reach in a 64 bit address space is pretty much completely irrelevant in both cases.
- brandmeyer 8y ago
  ADRP operates on the 4kB page of the pc (by truncation), not the entire pc. RISC-V could have implicitly added 2k in auipc and balanced out the bias. But they didn't.
  - brucehoult 8y ago
    I know how ADRP operates. It's symmetric about the truncated PC. It's not symmetric about the actual PC. As I said in the last post.
    - brandmeyer 8y ago
      I think you are misunderstanding the benefit of having symmetric reach by the page. On AArch64, you can define a 2 GB contiguous slice of address space, built up out of whatever page size you find convenient for your system and plant a relocatable binary into it, up to 2 GB of size. Any instruction anywhere in the last page can reach any address in the first page, and vice versa. In RISC-V, if you try to do the same thing, you'd find that while any instructions in the last page can reach any address in the first page with room to spare. But some instructions in the first page cannot reach portions of the last page. Sure, it doesn't matter most of the time. It isn't ever really an obstacle in practice for the feller writing application code for the platform. But the linker has to be aware of it in the 'medium' code model as a special case for just this particular platform. Somebody had to write that special case to work around the hardware.