4 ms·

> I can say that there are differences in loading large (48-64 bit) arbitrary constants without a pool. How arbitrary is arbitrary? ARMv7's Thumb2 format imme

> I can say that there are differences in loading large (48-64 bit) arbitrary constants without a pool. How arbitrary is arbitrary? ARMv7's Thumb2 format immediates are composed of a 8-bit field shifted by up to 5 bits. So you can form any 32-bit variable, but with limited precision. ARMv8 modified immediates can describe a contiguous run of ones followed by a contiguous run of zeros, and SWAR variations of the same. So you can describe things like a repeating 0x3f... for example. Do either of those formats encompass the kinds of literals that you need in the V8 JIT? > so you can use pc-relative addressing ... at a penalty of one word Since the RISC-V PC-relative addressing capabilities are similar to ARMv8 (adrp) and x86-64 (rip-relative addressing), I would have though that this is basically a non-problem. You pay one more live register to hold the page address, but you also get more registers, so I would think it mostly washes out. Where do you pay a penalty?

microcolonel 8y ago
> How arbitrary is arbitrary? ARMv7's Thumb2 format immediates are composed of a 8-bit field shifted by up to 5 bits. So you can form any 32-bit variable, but with limited precision. When it comes to encoding the address of an entry point, every bit of precision you lose (above the first two or three) in the address loses you memory compactness (and adds a certain amount of complexity to compilation and relocation). On the ARM and AArch64 V8 ports they use a constant pool for target addresses, on RISC-V you can probably just use AUIPC to compute the target address in place with no pool address register. You can, of course, do the exact same thing on RISC-V that they do in the ARM ports, but RISC-V has the considerable advantage of four extra bits (totalling 20) in U immediates vs. MIPS (16-bit U immediates), and eight extra bits vs. ARM in some cases (though ARM's immediate encodings are various and sundry, and produce a huge variety of corner cases and microoptimizations which are mostly useless to JITs [in my mostly amateur opinion]; to a lesser extent MIPS also has some interesting features for loading immediates which make up for the shortfalls in AOT code, but are harder [it seems to me, an amateur] to use effectively in a JIT).
- brandmeyer 8y ago
  AArch64 uses adrp in almost exactly the same way that RISC-V uses auipc to access literal pools. It isn't a strongly distinguishing feature between those architectures. The difference between them is that ADRP computes a 4 kB page-aligned pc-relative address, which complements the 12-bit unsigned address offsets in its base+disp addressing mode to get a uniform +(2 GB -1) to -2GB reach. RISC-V doesn't compute a page-aligned address, in order to partially compensate for the use of signed offsets in its base+disp12 addressing mode. I say partially because RISC-V's PC-relative reach remains asymmetric +(2 GB - 2k - 1) to -(2 GB + 2k), but that probably doesn't matter much as long as you establish an appropriate red zone. ARM distinguishes immediate operands used for data processing and immediate operands used for address generation. The alternative formats I was referring to are mostly just available for the logical operations (although Thumb2 sometimes also uses them for arithmetic). I was thinking that they might make pointer tagging a smidge easier to deal with. *edit: Whoops, 12-bit signed, not 10-bit signed on the asymmetry of the RISC-V reach.
  - brucehoult 8y ago
    Your figures seem a little off there. Yes, RISC-V is a little asymmetric, with the AUIPC being able to subtract exactly 2 GB from the PC or add 2GB-4KB to it, and then a jalr/lb/sb can subtract an additional 2 KB or add 2KB-1. But the AArch64 adrp is also asymmetric because the relative reach depends on where in the 4 KB page the original PC is. It's only symmetric if the PC is 4 KB aligned. If you're part way through the page then there is more -ve reach and less +ve reach. A couple of KB fuzziness in what is basically a 32 bit reach in a 64 bit address space is pretty much completely irrelevant in both cases.
    - brandmeyer 8y ago
      ADRP operates on the 4kB page of the pc (by truncation), not the entire pc. RISC-V could have implicitly added 2k in auipc and balanced out the bias. But they didn't.
      - 8y ago

microcolonel 8y ago

> How arbitrary is arbitrary? ARMv7's Thumb2 format immediates are composed of a 8-bit field shifted by up to 5 bits. So you can form any 32-bit variable, but with limited precision. When it comes to encoding the address of an entry point, every bit of precision you lose (above the first two or three) in the address loses you memory compactness (and adds a certain amount of complexity to compilation and relocation). On the ARM and AArch64 V8 ports they use a constant pool for target addresses, on RISC-V you can probably just use AUIPC to compute the target address in place with no pool address register. You can, of course, do the exact same thing on RISC-V that they do in the ARM ports, but RISC-V has the considerable advantage of four extra bits (totalling 20) in U immediates vs. MIPS (16-bit U immediates), and eight extra bits vs. ARM in some cases (though ARM's immediate encodings are various and sundry, and produce a huge variety of corner cases and microoptimizations which are mostly useless to JITs [in my mostly amateur opinion]; to a lesser extent MIPS also has some interesting features for loading immediates which make up for the shortfalls in AOT code, but are harder [it seems to me, an amateur] to use effectively in a JIT).

brandmeyer 8y ago
AArch64 uses adrp in almost exactly the same way that RISC-V uses auipc to access literal pools. It isn't a strongly distinguishing feature between those architectures. The difference between them is that ADRP computes a 4 kB page-aligned pc-relative address, which complements the 12-bit unsigned address offsets in its base+disp addressing mode to get a uniform +(2 GB -1) to -2GB reach. RISC-V doesn't compute a page-aligned address, in order to partially compensate for the use of signed offsets in its base+disp12 addressing mode. I say partially because RISC-V's PC-relative reach remains asymmetric +(2 GB - 2k - 1) to -(2 GB + 2k), but that probably doesn't matter much as long as you establish an appropriate red zone. ARM distinguishes immediate operands used for data processing and immediate operands used for address generation. The alternative formats I was referring to are mostly just available for the logical operations (although Thumb2 sometimes also uses them for arithmetic). I was thinking that they might make pointer tagging a smidge easier to deal with. *edit: Whoops, 12-bit signed, not 10-bit signed on the asymmetry of the RISC-V reach.
- brucehoult 8y ago
  Your figures seem a little off there. Yes, RISC-V is a little asymmetric, with the AUIPC being able to subtract exactly 2 GB from the PC or add 2GB-4KB to it, and then a jalr/lb/sb can subtract an additional 2 KB or add 2KB-1. But the AArch64 adrp is also asymmetric because the relative reach depends on where in the 4 KB page the original PC is. It's only symmetric if the PC is 4 KB aligned. If you're part way through the page then there is more -ve reach and less +ve reach. A couple of KB fuzziness in what is basically a 32 bit reach in a 64 bit address space is pretty much completely irrelevant in both cases.
  - brandmeyer 8y ago
    ADRP operates on the 4kB page of the pc (by truncation), not the entire pc. RISC-V could have implicitly added 2k in auipc and balanced out the bias. But they didn't.
    - 8y ago