4 ms·
For TR kind of. In the newer models only half the cores have direct access to a DDR channel. This shows in memory bounded benchmarks, but Epyc (server line) ele
by valarauca1 8y ago
For TR kind of. In the newer models only half the cores have direct access to a DDR channel. This shows in memory bounded benchmarks, but Epyc (server line) elevates this problem by have 8 (!!) memory channels, instead of the consumer TR’s 4.
Ultimately it depends on how cache friendly your workload is.
The 32c/64t is kind of a marketting gimmick selling binned Eypcs. If your doing memory bound HPC consider the 16c/32t model for roughly equal performance at a lower price.