4 ms·
I like their description of r0 as "limited use." There was some parody Twitter account with "new PowerPC instructions," one of which was mscdfr0 -- Means Someth
by classichasclass 8y ago
I like their description of r0 as "limited use." There was some parody Twitter account with "new PowerPC instructions," one of which was mscdfr0 -- Means Something Completely Different For Register 0. See https://twitter.com/ppcinstructions https://twitter.com/ppcinstructions for others (I'm not the author).
For those who don't get the joke, certain instructions like addi r0,r0,1 (encoded as addi 0,0,1) actually get turned into addi r0,0,1 -- instead of adding one to the contents of r0, they add one to zero, putting one in r0. This is to facilitate loading immediates, so a typical "load32" does an addis (same r0 limitation) to load the upper 16 bits followed by an ori (doesn't) to load the bottom.
This is maddening if you don't watch what you're doing, which is why RISC architectures that make a register explicitly always zero are sometimes less obnoxious (MIPS).
The article is, however, disingenuous about branching. Virtually any PPC (dis)assembler worth its salt will use extended mnemonics for the bc instructions the author complains about. Plus, you can branch on arbitrary bits in the condition register fields, which the bzero32 routine in Mac OS X uses to great effect (mtcrf 0x01,r4 puts the lower four bits into the condition field, and then it just tests each individual bit with a bf branch -- no compares needed!).
- notanotherone 8y agor0 was 0 only for addi/ addis and as rA=0 in EA calc for load/store, so you got 32 registers to store things into. The assembler should have implemented the simplified mnemonics. addis/addi was the suggested way to load a 32-but value in the Compiler Writer's Guide to take advantage of some mythical 3-input adder hardware, but was there ever an implementation that actual had one and a fetch/issue that supported it? Not in 603/604 afaict. ETA: [stuff about mtcr serialization which I misremembered.] The early stuff had low penalty branch mispredicts, so you would just do andi. or cmpi and however many branches. SPR numbering included non-problem state (privileged) registers. That's why it's sparse looking from user space.
- anyfoo 8y ago> The article is, however, disingenuous about branching. Virtually any PPC (dis)assembler worth its salt will use extended mnemonics for the bc instructions the author complains about. I sort of got that from the article, though: The official PowerPC assembly syntax is confusing, so (dis)assemblers added some extensions to make it more readable/writable. E.g.: "This is ridiculously confusing,² so nobody uses the purely numeric names. People call them r0 through r31. (Some assemblers call them r.0 through r.31.)"
- perl4ever 8y agoOld MacDonald had a PowerPC, eieio... https://en.wikipedia.org/wiki/Enforce_In-order_Execution_of_I/O https://en.wikipedia.org/wiki/Enforce_In-order_Execution_of_... ...I also liked instructions like rlwinm and stfsux. There was no "stfu" but it does sound plausible...
- gcb0 8y agoI am sorry for game and compiler developers. or is there any other group that cares about this today?
- kev009 8y agoIf you want to get really skilled at debugging, symbolic debuggers often break down in ways that are easily worked through by reading disassembly. Reverse engineering is a related and more elaborate extension of that. Finally, certain types of development are done partially with native use of the ISA even if the majority is done in a higher level language like implementing atomics and related lock free algorithms, bootstrap code for systems software, multimedia and compression codecs. It's useful and only a few days learning to have at least passive familiarity in the main ISA you use if you do anything that compiles down to native code for the first reason. It's also not that bad, I'd rather read assembly over modern javascript frameworks to be perfectly blunt.
- gcb0 8y agomost of the time I had to gdb something that was broken (apache on all my last times) I was looking for IO instruction at the wrong time instead of bugs in pointers usage, but yeah, I do see your point (no pun intended). I can clearly see eioio causing some of the performance/race conditions I was hunting down recently (which thankfully was NOT on ppc :)
- ido 8y agoa tiny, faint silver of a percent of all game developers would ever need to write assembly code these days, PPC or otherwise. Even on low-end phones you can safely use c.