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It's really not a meme that the tools suck. They still suck. They suck a lot less than they used to but they still suck. The latest version of Vivado still does

by slivym 8y ago

It's really not a meme that the tools suck. They still suck. They suck a lot less than they used to but they still suck. The latest version of Vivado still doesn't properly support basic constructs of systemverilog [1]. That doesn't fly in the world of software engineers. The compile times are still in the order of hours, and there's no guarantee that you won't get to the end of your compile and find out either it didn't work, or it did something that you couldn't possibly have meant to happen. You don't know what went wrong because you've got a 27MB log file 97% of which is 'WARNING's. [1]:https://www.xilinx.com/support/answers/55135.html https://www.xilinx.com/support/answers/55135.html

tails4e 8y ago
Perhaps it's the case that EDA sucks full stop. I think in the general case that's true, but FPGA based EDA tools, by and large, are better than ASIC EDA tools, and much better than any open-source tool available - and they are essentially free. If you've every used the ASIC tools design-compiler or primetime, you'd see what a difference tools like Vivado have brought in terms of design visualization, ease of use, robustness, all while still being compatible with the industry standard constraints and file types, etc. The list of unspported items you showed is interesting but I'd imagine they rarely affect HW design and are more on the testbench / simulation only subset (except maybe arrays of interfaces). For any HW design I've done Vivado has been well able to handle it. In fact, I've used Vivado to 'sanity check' RTL thats intended for an ASIC flow. Runtimes are long, but I guarantee if you look at the runtime of any opens source synthesis tool you'd get an order of magnitude worse, with worse results. The FPGAs these tools are handling are also huge compared to ten years ago, so while they have progressed in a direct comparison, it looks like they have not if you're later devices. The one bugbear I have is that DRCs are not checked as early as possible, and only at the end are some things flagged, like and unconstrained IO port. Things that can be caught earlier should be, in all cases.

by slivym 8y ago

tails4e 8y ago

Perhaps it's the case that EDA sucks full stop. I think in the general case that's true, but FPGA based EDA tools, by and large, are better than ASIC EDA tools, and much better than any open-source tool available - and they are essentially free. If you've every used the ASIC tools design-compiler or primetime, you'd see what a difference tools like Vivado have brought in terms of design visualization, ease of use, robustness, all while still being compatible with the industry standard constraints and file types, etc. The list of unspported items you showed is interesting but I'd imagine they rarely affect HW design and are more on the testbench / simulation only subset (except maybe arrays of interfaces). For any HW design I've done Vivado has been well able to handle it. In fact, I've used Vivado to 'sanity check' RTL thats intended for an ASIC flow. Runtimes are long, but I guarantee if you look at the runtime of any opens source synthesis tool you'd get an order of magnitude worse, with worse results. The FPGAs these tools are handling are also huge compared to ten years ago, so while they have progressed in a direct comparison, it looks like they have not if you're later devices. The one bugbear I have is that DRCs are not checked as early as possible, and only at the end are some things flagged, like and unconstrained IO port. Things that can be caught earlier should be, in all cases.