Exactly, synthesizable HDL code means code that can be actually translated into logic gates inside an FPGA [1]. Not every HDL instruction is synthesizable. Ver

Exactly, synthesizable HDL code means code that can be actually translated into logic gates inside an FPGA [1]. Not every HDL instruction is synthesizable. Verilog and VHDL have extensive support for non-synthesizable code, which are used for verification, simulation, testing, etc - e.g., [2]. [1] https://en.wikipedia.org/wiki/Logic_synthesis https://en.wikipedia.org/wiki/Logic_synthesis [2] https://www.nandland.com/articles/synthesizable-vs-non-synthesizable-code-fpga-asic.html https://www.nandland.com/articles/synthesizable-vs-non-synth...