I'll give you a simple proof by appeal to absurdity: Single instruction-set computers totally do exist, but perform very poorly. So clearly, the ISA does matt

I'll give you a simple proof by appeal to absurdity: Single instruction-set computers totally do exist, but perform very poorly. So clearly, the ISA does matter in the extreme ends. That said, it is true that the data processing features available in modern ISA's have largely converged towards each other. ARM, Power, and x86 all have instructions for popcount, leading zero count, byte reversal, and efficient multiword arithmetic. ARMv8 and x86 both have multiplication in GF(2), too. RISC-V doesn't have any of those things. And while its true that the vast majority of program code out there doesn't use it directly, the vast majority of total systems do use them somewhere important. Modern schedulers and memory allocators rely on fast leading zero count. Crypto codes rely on GF(2) and multiword arithmetic. Anything dealing with network packet processing needs low-latency byte reversal, and so on. RISC-V's failure to include those features in the general-purpose profile will absolutely hurt its adoption for general-purpose compute.