I see your point about intensives. However I have to disagree on your opinion on the hardware. RISC-V was specifically designed to be able to do low end very w

I see your point about intensives. However I have to disagree on your opinion on the hardware. RISC-V was specifically designed to be able to do low end very well. The whole encoding for example is optimized to a tiny amount of space. The overall instruction set again is designed to use minimum amount of space as well. There is a whole project about 'ultra low power processors' at ETH Zürich [1]. They have specifically selected RISC-V because it fit their needs so well and they produce cores that beat available ARM and MIPS cores specially on energy. IBM selected a RISC-V core for their project in 'Next-Generation Edge Computing' [2]. So it seems to me that small and simple really does pay of when going to very tiny cores. [1] https://www.pulp-platform.org/ https://www.pulp-platform.org/ [2] https://content.riscv.org/wp-content/uploads/2018/05/16.10-16.25-Seiji-Munetoh-IBM-Japan.pdf https://content.riscv.org/wp-content/uploads/2018/05/16.10-1...