First of all, the ISA does not need implementations to be non-hypothetical. The ISA is defined and frozen and that includes most of the extensions. There have

First of all, the ISA does not need implementations to be non-hypothetical. The ISA is defined and frozen and that includes most of the extensions. There have been 100s of tap-outs from different RISC-V chips. So clearly its not hypothetical in that sense either. > - They deliberately choose to leave parts of the instruction space open. That’s good for extensibility, but must have a negative effect on code density. and > - They are extremely liberal in allowing implementations to mix and match instruction set extensions. That's not a problem that is a feature. It was specifically designed to extendable and to have many different extensions so implementers could pick and choice of what they want. RISC-V is designed to work for close to sensor tiny chips all the way to super-computers and everything in between. To be able to handle that with one instruction set you can not force every deeply embedded chip to implement all the features. To combat the explosion theoretical ISA the foundation defines profiles. Profiles are designed to select standard configurations for specific applications or groups of users. For example, RISC-V for Linux uses 'RV64GC' and all Linux software uses it. However if you use RISC-V internally you can pick whatever you like for your needs.