3 ms·
Nice, I hadn't looked at RISC-V before. The operation of FENCE.I scares me a little: > FENCE.I does not ensure that other RISC-V harts’ instruction fetches wi
by PDoyle 8y ago
Nice, I hadn't looked at RISC-V before.
The operation of FENCE.I scares me a little:
> FENCE.I does not ensure that other RISC-V harts’ instruction fetches will observe the local hart’s stores in a multiprocessor system. To make a store to instruction memory visible to all RISC-V harts, the writing hart has to execute a data FENCE before requesting that all remote RISC-V harts execute a FENCE.I
Yikes. That sounds cumbersome for multithreaded code patching systems, like modern JIT compilers. (A "hart" here is a hardware thread.) Sounds like all threads must poll periodically to check whether they should run a FENCE.I, and when they do so, they report that they've done it. Doesn't sound like a lot of fun to implement, though maybe better in software than hardware?
- rwmj 8y agoI don't know enough to say if this is accurate or not. However there are working groups reviewing the memory model[1] (also implementing fast ISRs[2]) so if there are performance problems in this area then they're being looked at. [1] https://content.riscv.org/wp-content/uploads/2018/05/14.25-15.00-RISCVMemoryModelTutorial.pdf https://content.riscv.org/wp-content/uploads/2018/05/14.25-1... https://content.riscv.org/wp-content/uploads/2018/05/10.40-10.55-Daniel-Lustig.pdf https://content.riscv.org/wp-content/uploads/2018/05/10.40-1... [2] https://content.riscv.org/wp-content/uploads/2018/05/08.45-09.10-RISCV-20180509-FastInts.pdf https://content.riscv.org/wp-content/uploads/2018/05/08.45-0...