4 ms·
1. Heat dissipation is now ~n x m times worse where n is your transistor layer count. And where m is the increased thermal resistance* 2. Power delivery is now
by deepnotderp 8y ago
1. Heat dissipation is now ~n x m times worse where n is your transistor layer count. And where m is the increased thermal resistance*
2. Power delivery is now ~n times worse where n is your transistor layer count. *
3. Connections between chips are very slow, power hungry and expensive. Fabrication of "monolithic" 3D is temperature wise painful and usually results in crummier transistors.
With that being said, innovative 3D integration methods in specific applications can help a lot. Shameless plug: we at Vathys do this for deep learning chips.
* to a first order of approximation
- tormeh 8y agoThe heat can be tackled in part by pumping water through holes in the CPU. I believe it was IBM that came up with this. Can't tell if it's feasible or not.
- blackflame7000 8y agoI was thinking by either creating a temperature differential on a copper conductor to chill the cube from within or that the motherboard/walls would provide cooling from the pin side.
- deepnotderp 8y agoYes but microfluidics limits how thin each die can be.
- agumonkey 8y agoWhat about stacked heat vias ?
- deepnotderp 8y agoWhat are those? Do you mean something like thermal "dummy" vias?
- agumonkey 8y agoyeah, something imprinted in all layers so you could evacuate heat
- deaddodo 8y agoThey do use some 3D techniques inside dies. Tri-gate transistors and 3DICs, for insurance
- deepnotderp 8y agoYes well FinFETs and other non planar transistors are very different from what's being discussed here. Interestingly, FinFETs actually do suffer from a bit of a self heating effect although this usually isn't a problem for AC operation.