This is really exciting. I've thought about building a datapath on an FPGA that uses partial reconfiguration to synthesize new hardware blocks based on the math

This is really exciting. I've thought about building a datapath on an FPGA that uses partial reconfiguration to synthesize new hardware blocks based on the math being doing at a particular instant, and it sounds like DARPA wants to do that on steroids. Server CPUs coupled with FPGAs are already being used for a lot of interesting things and I think it makes a lot of sense to integrate together even tighter. I'm also really happy to hear that they're funding new EDA software that is actually smart. The best we have right now is some whitelist based rule checking for schematics and layout. I want full simulation, a perfect, proven parts library with symbols, footprints, 3D models, non-ideal SPICE models, and a thermal model for every part in existence, smart rule checking that looks not only for things like unconnected nets, but logic level mismatches and clock edges that are too fast. Little pieces of this exist already, but in my opinion, software for creating hardware is way behind software for creating software.