If you read up on the structure of an FPGA lookup table (LUT) in detail, you'll see that most of their size is taken up as memory. A Xilinx 7-series LUT6 Confi

If you read up on the structure of an FPGA lookup table (LUT) in detail, you'll see that most of their size is taken up as memory. A Xilinx 7-series LUT6 Configurable Logic Block (CLB) is a 64-entry 1-bit sram, read out with a 6-bit address. If you don't need the ability to reconfigure the system any more, you can hardwire each of those 64 entries to the VDD and VSS rails instead. Its not nearly as efficient as the circuits you can get with a set of dedicated logic cells, but its much more efficient than the baseline FPGA fabric. If the customer has already validated their logic on FPGA fabric, then its also much cheaper. You just ask these guys to "burn" it into an ASIC and you suddenly get a few hundred extra MHz. Why are they called 'vias'? Because ASIC layout is somewhat similar to PCB layout - transistors go on one layer, and there are a dozen or so layers of routing wires below them, with vias in between the layers. So you can replace the transistors that would have been implementing SRAM cells for read/write LUTs with vias to power/ground layers instead.