4 ms·
The mnemonics of RISC V are terribly thought out when compared to OpenSPARC or the legendary MC68000. Particullarly galling is the choice of dst, src rather tha
by Annatar 8y ago
The mnemonics of RISC V are terribly thought out when compared to OpenSPARC or the legendary MC68000. Particullarly galling is the choice of dst, src rather than src, dst (although that could be solved by using UNIX®️ version of as(1)). Terribly thought out design internally. Not that ARM is much better, mind you.
- kps 8y agoIf Intel has taught us anything about ISAs, it's that having a shitty one doesn't much hurt. If ARM has taught us anything about ISAs, it's that starting with a nice one doesn't mean it won't end up a mess. (There exist 32-bit ARM implementations with precisely zero opcodes in common.)
- microcolonel 8y agoOddly enough, these are among the least concerning, least permanent aspects of the specs; not sure why they bother you so much either. It's frankly not a whole lot different from MIPS, except lacking exposed delay slots, and a number of instructions that turn out not to have been used much. My biggest issue is with how many instruction bytes it can take to load an arbitrary 64-bit immediate without an IC, but that can be gotten around by using an IC.