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RISC-V is open instruction set, not open microarchitecture. You won't see high performance open source micrarchitectures that implements RISC-V core. Nobody i

RISC-V is open instruction set, not open microarchitecture. You won't see high performance open source micrarchitectures that implements RISC-V core. Nobody is going to invest $300-$500M to develop new competitive open source microarchitecture (patent free?) every 5-10 years for RISC-V that can compete with Intel, AMD and others.

nickik 8y ago
> You won't see high performance open source micrarchitectures that implements RISC-V core. You don't have to spend $300-$500 to get to a reasonable performance. There are multiple people who are interested in this. The EU and India have processor initiatives (including high perf) that will use RISC-V. Many universities, non-profits, companies will continue to work on the current open-source chips and combined with open source. Of course it will take time but blanked 'You won't see high performance open source micro-architectures' is just an assumption.
- Nokinside 8y ago
  Yes you have. It's completely different to design small volume ASIC chip with RISC-V processor and high volume microprosessor core that is cost effective. Processor initiative in EU and India have are providing R&D money for basic research and competence building for local companies. They will be customers, not manufacturers.
  - nickik 8y ago
    The EU and India will both build actual chips and those can be tapped out. They will also of course consume their own stuff. There are startups like Esperanto and many university groups and open source who are all interested. Of course you still need to find costumers for a mass tapeout, but once the whole linux tool-chain is running there are lots of potential applications and costumers.
ant6n 8y ago
That's like saying u won't see a general purpose, high performance, highly reliable open source operating system for servers and consumers, with a total development cost of more than a billion in terms of total person hours. Yet here we are.
- phkahler 8y ago
  And who would make a free Office suite? Or an open source tool chain (we have two now!), or EDA tools, web browser, audio/vide codecs, or.... Once you have a decent base and sufficient interest, peoples incremental changes will get there eventually.
  - vonmoltke 8y ago
    > Once you have a decent base and sufficient interest, peoples incremental changes will get there eventually. The size of a viable increment in a software project is much smaller than it is in a hardware project. Developing a functional, non-trivial microarchitecture requires significant capital expenditure and coordination of efforts. This requires at least a patron of some sorts to manage the process, where the requirements for that patron are much more significant than "somebody with a listserv".
    - debatem1 8y ago
      Nvidia is not ignorant of the realities of hardware design. Google spends capital to get what it wants. Western Digital is not just "somebody with a listserv". Once those players front the money for the ecosystem the incentive to coordinate is there on the fab side. With that in place and good simulation possible, the size of an incremental change is an exercise in release management.
- jasonkostempski 8y ago
  But software has basically no overhead to produce, improve, fix or deploy.
  - 8y ago
mtgx 8y ago
The EU has already chosen RISC-V as one of the two options for developing chips for its supercomputers: https://www.slideshare.net/insideHPC/european-processor-initiative-riscv https://www.slideshare.net/insideHPC/european-processor-init... I imagine China and India will eventually go with RISC-V, too. Maybe Nvidia will have "another go" at designing its own CPU microarchitecture, too, if they get tired of Arm's shenanigans. Nvidia has already chosen RISC-V for its GPU microcontroller.
- Nokinside 8y ago
  R&D from EU, China, Japan and India are not going to result open source microarchitectures. Government supports basic R&D but the end product will be commercial closed source IP and patented.
  - mlyle 8y ago
    https://bitbucket.org/casl/shakti_public https://bitbucket.org/casl/shakti_public
    - Nokinside 8y ago
      >While we do plan to tape out a few variants, given the foundry NDA requirements, we will not be able to publish any layout/backend data. But the ASIC syntesis and P&R data to teh extent possible will be published to allow others to replicate our ASIC flow.
lkcl 8y ago
> You won't see high performance open source micrarchitectures that implements RISC-V core. India's Shakti Core is a 6-stage pipeline that runs at 2.5ghz in 20nm and uses only 120mW. Their roadmap includes VLSI variants which will piss all over ARM and Intel, which is funny because the India Goverment has given them unlimited resources and backing to do exactly that. All entirely libre-licensed... starting here: https://bitbucket.org/casl/ https://bitbucket.org/casl/

nickik 8y ago

> You won't see high performance open source micrarchitectures that implements RISC-V core. You don't have to spend $300-$500 to get to a reasonable performance. There are multiple people who are interested in this. The EU and India have processor initiatives (including high perf) that will use RISC-V. Many universities, non-profits, companies will continue to work on the current open-source chips and combined with open source. Of course it will take time but blanked 'You won't see high performance open source micro-architectures' is just an assumption.

Nokinside 8y ago
Yes you have. It's completely different to design small volume ASIC chip with RISC-V processor and high volume microprosessor core that is cost effective. Processor initiative in EU and India have are providing R&D money for basic research and competence building for local companies. They will be customers, not manufacturers.
- nickik 8y ago
  The EU and India will both build actual chips and those can be tapped out. They will also of course consume their own stuff. There are startups like Esperanto and many university groups and open source who are all interested. Of course you still need to find costumers for a mass tapeout, but once the whole linux tool-chain is running there are lots of potential applications and costumers.

ant6n 8y ago

That's like saying u won't see a general purpose, high performance, highly reliable open source operating system for servers and consumers, with a total development cost of more than a billion in terms of total person hours. Yet here we are.

phkahler 8y ago
And who would make a free Office suite? Or an open source tool chain (we have two now!), or EDA tools, web browser, audio/vide codecs, or.... Once you have a decent base and sufficient interest, peoples incremental changes will get there eventually.
- vonmoltke 8y ago
  > Once you have a decent base and sufficient interest, peoples incremental changes will get there eventually. The size of a viable increment in a software project is much smaller than it is in a hardware project. Developing a functional, non-trivial microarchitecture requires significant capital expenditure and coordination of efforts. This requires at least a patron of some sorts to manage the process, where the requirements for that patron are much more significant than "somebody with a listserv".
  - debatem1 8y ago
    Nvidia is not ignorant of the realities of hardware design. Google spends capital to get what it wants. Western Digital is not just "somebody with a listserv". Once those players front the money for the ecosystem the incentive to coordinate is there on the fab side. With that in place and good simulation possible, the size of an incremental change is an exercise in release management.
jasonkostempski 8y ago
But software has basically no overhead to produce, improve, fix or deploy.
- 8y ago

mtgx 8y ago

The EU has already chosen RISC-V as one of the two options for developing chips for its supercomputers: https://www.slideshare.net/insideHPC/european-processor-initiative-riscv https://www.slideshare.net/insideHPC/european-processor-init... I imagine China and India will eventually go with RISC-V, too. Maybe Nvidia will have "another go" at designing its own CPU microarchitecture, too, if they get tired of Arm's shenanigans. Nvidia has already chosen RISC-V for its GPU microcontroller.

Nokinside 8y ago
R&D from EU, China, Japan and India are not going to result open source microarchitectures. Government supports basic R&D but the end product will be commercial closed source IP and patented.
- mlyle 8y ago
  https://bitbucket.org/casl/shakti_public https://bitbucket.org/casl/shakti_public
  - Nokinside 8y ago
    >While we do plan to tape out a few variants, given the foundry NDA requirements, we will not be able to publish any layout/backend data. But the ASIC syntesis and P&R data to teh extent possible will be published to allow others to replicate our ASIC flow.

lkcl 8y ago

> You won't see high performance open source micrarchitectures that implements RISC-V core. India's Shakti Core is a 6-stage pipeline that runs at 2.5ghz in 20nm and uses only 120mW. Their roadmap includes VLSI variants which will piss all over ARM and Intel, which is funny because the India Goverment has given them unlimited resources and backing to do exactly that. All entirely libre-licensed... starting here: https://bitbucket.org/casl/ https://bitbucket.org/casl/