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Intel's looking at doing this, with an interface from the southbridge and probably soon from the CPU itself. I think eventually for low-end PCs and netbooks, C
by Andys 16y ago
Intel's looking at doing this, with an interface from the southbridge and probably soon from the CPU itself. I think eventually for low-end PCs and netbooks, CPUs will just have big L3 (DRAM) caches, and flash behind that, and no system DRAM at all.
- pjscott 16y agoIf they can get the power of the CPU down low enough, they could probably bolt on a DRAM layer, right on top of the CPU die, and connect them with through-silicon vias. Your L3 cache could have the same die size as the CPU, and the connection to the CPU could be very fast, both in bandwidth and in latency. Actually, these "low-end PCs and netbooks" are sounding like speed demons, the more I think about them.
- Andys 16y agoOn-die DRAM cache is a solved problem (though IBM probably owns the patent). DRAM itself is not that power intensive that it would present a problem for the CPU TDP.
- pjscott 16y agoI checked, and apparently they've now invented on-die DRAM that doesn't require extra processing steps. Nice! Die stacking would still have advantages in reducing wire delay (thus reducing the L2 miss penalty) and increasing the yield.