ARM is playing a very, very dumb game here. Do they seriously think any prospective RISC-V user has not taken this information into account? Whomever goes on to

ARM is playing a very, very dumb game here. Do they seriously think any prospective RISC-V user has not taken this information into account? Whomever goes on to design an ASIC probably knows what they are getting into well enough. ARM would be much wiser to embrace RISC-V early, spearheading this effort and bringing RISC-V users into their tools and ecosystem.