Yep, all you need to do is build a massive out-of-order superscalar pipeline with 8 to 10 execution ports and a very large reorder buffer (150 to 200 uops). And

Yep, all you need to do is build a massive out-of-order superscalar pipeline with 8 to 10 execution ports and a very large reorder buffer (150 to 200 uops). And idealy toss in hypertreadding. Intel has done it with x86, IBM have done it with POWER, AMD have done it with x86 (more or less independently to Intel), Sun/Oracle have done it with SPARC, Apple have done it with ARM and most recently it looks like ARM's Cortex A76 is joining the league. All these designs look very similar, they are basically variatins on the same archtechure with different front ends.