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An FPGA is not an ASIC. Latches are totally valid design choices and they take less silicon area if doing a custom layout. The thing is that an FPGA has a lot o
by analognoise 8y ago
An FPGA is not an ASIC. Latches are totally valid design choices and they take less silicon area if doing a custom layout. The thing is that an FPGA has a lot of time/money spent on getting the clock network and tooling for that clock network correct in a flopped digital style, and you obviate that by trying to force latches.