4 ms·
Yeah, pretty interesting. And I remember the TA in my digital logic lab slapping our wrists if we tried to use latches like that.
by brian-armstrong 8y ago
Yeah, pretty interesting. And I remember the TA in my digital logic lab slapping our wrists if we tried to use latches like that.
- analognoise 8y agoAn FPGA is not an ASIC. Latches are totally valid design choices and they take less silicon area if doing a custom layout. The thing is that an FPGA has a lot of time/money spent on getting the clock network and tooling for that clock network correct in a flopped digital style, and you obviate that by trying to force latches.