3 ms·
This page gives the first low-level explanation I've ever found for why the 6502 requires a two-phase clock.
by phaedrus 8y ago
This page gives the first low-level explanation I've ever found for why the 6502 requires a two-phase clock.
- brian-armstrong 8y agoYeah, pretty interesting. And I remember the TA in my digital logic lab slapping our wrists if we tried to use latches like that.
- analognoise 8y agoAn FPGA is not an ASIC. Latches are totally valid design choices and they take less silicon area if doing a custom layout. The thing is that an FPGA has a lot of time/money spent on getting the clock network and tooling for that clock network correct in a flopped digital style, and you obviate that by trying to force latches.
- FullyFunctional 8y agoI'm not a EE but four transistors for a D-FF is hard to beat. Z-80 other contemporaries also used dual phase clocks. Obviously the downsides outweighed the transistor overhead eventually. There was a "modern" instantiation of this by Intrinsity (got acquired by Apple) whose "FAST-14" [1] dynamic logic used a four-phase clock. That was pretty cool and they had some (for the time) insanely fast products. I wonder if that logic style would have been feasible in the 6502's time frame. [1] https://en.wikichip.org/wiki/intrinsity/fast14 https://en.wikichip.org/wiki/intrinsity/fast14
- GeorgeTirebiter 8y agoThe Z-80 has a single-phase clock, which was one of its selling features. https://en.wikipedia.org/wiki/Zilog_Z80 https://en.wikipedia.org/wiki/Zilog_Z80 The 8008 and 8080 use dual-phase clocks.
- FullyFunctional 8y agoD'oh. Thanks for the correction. I was indeed thinking of 8080.