Its quite a bit more complicated than "bootloader" might make it sound. From the mailing list: "The original boot chain on the SiFive FU540 looks like this:

Its quite a bit more complicated than "bootloader" might make it sound. From the mailing list: "The original boot chain on the SiFive FU540 looks like this: MSEL (ROM0) -> ZSBL (ROM1) -> FSBL (SPI) -> bbl (SPI/SD) -> Linux Where the individual pieces mean this: MSEL: The "Mode select" ROM, consisting of a register that represents the state of four pins on the chip, and six instructions, which jump to the selected boot device or ZSBL. Fully documented (with an instruction listing) in the manual. ZSBL: The "Zeroth stage bootloader", several kilobytes of code in ROM, which parses a GPT header on SPI flash or an SD card and loads the next stage. Short, high-level documentation in the manual; I haven't seen the source code. FSBL: The "First stage bootloader", where interesting things like RAM init happen. High-level documentation in the manual; I haven't seen the source code. BBL: The "Berkeley bootloader". Its most important role, as far as I understand it, is to implement the SBI. The source code is public. See also chapter 6 (Boot process) of the FU540-C000 Manual[4]. With the unfinished coreboot port, I want it to look like this (although a lot of work has to be done on coreboot first, and I'm currently not actively working on that, for a few months): MSEL (ROM0) -> ZSBL (ROM1) -> coreboot (+bbl?) -> Linux, or MSEL (ROM0) -> coreboot (+bbl?) -> Linux ZSBL can be skipped, so you don't need to run closed source ROM code, at least as far as the hardware is concerned. (And note that this is just the situation on this particular SoC. Other SoCs from SiFive or other vendors may boot differently.)"