The way I (not EE) understand it the size of a process considers just one dimension. So transistors can be tightly packed along that axis and less tightly packe

The way I (not EE) understand it the size of a process considers just one dimension. So transistors can be tightly packed along that axis and less tightly packed along the other axis of a wafer. Have the gate pitch / interconnect in the range of 40-54nm hit a more difficult limit than the 7nm aspect? It seems like there is significant space for improvement in those dimensions where you could still double density. Should process nodes be referred to as 7nm x 54nm where new generations drop gate pitch too? Is there something inherent to the process that fixes the other dimensions when you have a "7nm" node for that particular metric?