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That approach has (sort of) been tried before for superscalar architectures. VLIW architectures were the Next Big Thing in the early 1990s. The general idea is
by zik 8y ago
That approach has (sort of) been tried before for superscalar architectures. VLIW architectures were the Next Big Thing in the early 1990s. The general idea is that the machine code explicitly told the CPU what to do with each of its execution units. It seems like a good idea. Intel released their i860 processor and waited for the cash to roll in.
The trouble was that because the machine code is pretty specific to the internal structure of the CPU every time they released a new major revision of the CPU the existing executables all had to be recompiled. All of their customers needed to get an entirely new OS, new third party software, they had to recompile all their own code, everything. This proved too much of a burden for many and popularity of the architecture suffered.
The other problem of these kinds of architectures is that they're quite inefficient at encoding code with lacks inherent parallelism. The instructions are long and most of them have to be NOPs if most of the execution units are idle - which is a lot of the time. This code bloat in turn wastes memory bandwidth and instruction cache space, making them overall not as efficient at using precious cache space as architectures with more compact instructions.
- gm-conspiracy 8y agoKind of interesting to thing of the CPU as just another peripheral.
- ksec 8y agoThat was in the 90s though. We haven't had much "design" in CPU for 5 years. We are stuck with 4-5Ghz max, IPC seems to have its limit. And now we ran into security issues with too much clever hardware optimisation. And it seems recompiling is relatively easy enough for servers? Where everything are in controlled environment?
- chx 8y ago> And now we ran into security issues with too much clever hardware optimisation. I contest "now". It seems we ran into security issues at latest with Sandy Bridge (lazy FP) but many even earlier.
- spamizbad 8y agoThere have been some remarkable enhancements toward cache coherency and feeding data to large core counts while keeping latency from completely going crazy.
- deepnotderp 8y agoThose weren't the only problems with VLIW (and more specifically Itanium-type VLIW). Recompiling and increased code size would've been fine if that were the only concerns. The big problem is that so far, in general purpose workloads (the type with heavy control flow and gnarly memory access), VLIW was never able to match OoO in performance in terms of extracting enough ILP.