3 ms·
Even 15 decoders are a pinprick on the core’s area—at least when I saw die area for LRB. Fetch & schedule we’re a bit larger. Most of the core area was register
by thechao 8y ago
Even 15 decoders are a pinprick on the core’s area—at least when I saw die area for LRB. Fetch & schedule we’re a bit larger. Most of the core area was register files & floating-vector logic.
- bogomipz 8y ago>."..at least when I saw die area for LRB" What is LRB?
- woadwarrior01 8y agoProbably Larrabee, Intel’s cancelled GPGPU with an x86 ISA.
- brandmeyer 8y agoIn fairness, Larrabee was originally an in-order design.
- gpderetta 8y agoIt was also a simpler core, which means that for a complex OoO monster, the decoder would be an even smaller area. The OoO instruction scheduler would be a significant chunk, but that has nothing to do with being x86.