Sounds like a nightmare, this is basically the type system of vanilla verilog: Everything is just a bitvector of a certain length, each bit can have four states

Sounds like a nightmare, this is basically the type system of vanilla verilog: Everything is just a bitvector of a certain length, each bit can have four states X,Z,0,1, so that it allows you to assign to a 32bit vector a 16bit vector resulting in the upper 16bit to be undefined. System verilog added structs, but if you declare them packed they allow unstructured assignment. Overall it is a complete nightmare given the fact that at the end you will tape out a chip that might cost >1 million to produce.