7 ms·
The lack of multi-register store and load is one is one of my biggest gripes with the RISC-V ISA. It just hurts to see the compiler waste 32 x2 bytes just to sa
by TomVDB 8y ago
The lack of multi-register store and load is one is one of my biggest gripes with the RISC-V ISA. It just hurts to see the compiler waste 32 x2 bytes just to save and restore register context. (It matters a lot when you have a little CPU with 4KB of program RAM.)
What does it matter that it’s not pure?
- thesz 8y agoBecause if it is ot pure you will have trouble having differrent implementations of same ISA. Imagine implementing same feature for superscalar OoO or for version where pipeline length is only two or one cycle. Being a software dev I also designed CPUs. I know what I am talking about. For you having 4K IRAM - use stack machine. You'd be better off.