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Article says "CPU does not fit FPGA synthesis very well and uses almost whole thing". People serious about prototyping usually get daughterboards for FPGA and/
by thesz 8y ago
Article says "CPU does not fit FPGA synthesis very well and uses almost whole thing".
People serious about prototyping usually get daughterboards for FPGA and/or FPGA stacks specifically to prototype big things with CPUs. The buses can go outside of main FPGA with CPU and into other things. I know at least one big SoC project which went that way.
I also think that having an ARM core in FPGA is a vendor lock in. For example, you cannot use AMBA/APB/AXB and other ARM buses with ARM CPU core in your design without paying ARM for license for these buses. It is not clear to me whether Zynq users have to pay for these buses and it may be case that they have to. Finally, ARM core in the prototype naturally extends into ARM core in the final product.
ARM itself is not very nice design from contemporary point of view. I expressed my dissatisfaction with ARM ISA many times here and just let me start with two points: 1) ARM is not RISC (multiregister load/store execute in several clocks) and 2) too much of initial design of first ARM (which was not planned for longterm evolution) is visible in ISA.
Basically, they put outdated (even for 2010) core design and used valuable silicon area so users have to use that instead of much more capable contemporary designs. Instead of trying to figure out how to change typical FPGA elements and layouts for CPUs to be more synthesable (which may bring benefits in other places), they decided to use that ARM thing.
I am deeply disappointed with that path.
- adwn 8y ago> ARM itself is not very nice design from contemporary point of view. [...] they decided to use that ARM thing ARM CPUs are the de-facto standard in the embedded world (except for simple 8-bit MCUs), so what should Xilinx have done? Design their own, proprietary CPU architecture and ISA? Choose some other architecture with 2% market share? Both paths would have led to the immediate death of the whole product line. > 1) ARM is not RISC (multiregister load/store execute in several clocks) So? Who cares? > 2) too much of initial design of first ARM (which was not planned for longterm evolution) is visible in ISA. Ah, yes, technological purism – the quickest way to practical irrelevance.
- planteen 8y ago> ARM CPUs are the de-facto standard in the embedded world (except for simple 8-bit MCUs), so what should Xilinx have done? Design their own, proprietary CPU architecture and ISA? Choose some other architecture with 2% market share? Both paths would have led to the immediate death of the whole product line. Totally agree. IIRC, didn't Xilinx have another hard core CPU+FPGA design before the Zynq using a PowerPC? PPC is largely irrelevant these days. The high-performance embedded space is dominated by ARM today with x86 and PPC taking the rest. There's no way Xilinx would choose x86 with Intel owning Altera. Maybe in 5-10 years RISC-V will start to eat some of ARM's share, but that remains to be seen.
- 0xcde4c3db 8y ago> didn't Xilinx have another hard core CPU+FPGA design before the Zynq using a PowerPC? Yes; more than one. There were at least the Virtex II Pro, Virtex 4 FX, and Virtex 5 FX families.
- thesz 8y agoIntel didn't own Altera in 2010.
- thesz 8y agoRISC-V started 2010, the year Zynq was dreamed up. Candence bought XTensa (much less than 2%) and I know of several products using their cores. My arguments about ARM CPU inferiority are about ARM CPU inferiority and related vendor lock-in. I summarize them: for your substantial money you get inferior CPU you cannot improve much, for prototyping and then for product, with highly aggressive pricing when you want to run ASIC.
- adwn 8y ago> RISC-V started 2010, the year Zynq was dreamed up. Exactly: much too late for Zynq, and still a minuscule market share even 8 years later. > for your substantial money you get inferior CPU Wrong, and furthermore, you still didn't get the point: It's not about theoretical technological perfection, but about the surrounding ecosystem, tooling, related IP, available expertise, and support. > CPU you cannot improve much Also wrong, and irrelevant for 99% of use cases. > with highly aggressive pricing when you want to run ASIC Irrelevant for 99% of FPGA designs.
- TomVDB 8y agoThe lack of multi-register store and load is one is one of my biggest gripes with the RISC-V ISA. It just hurts to see the compiler waste 32 x2 bytes just to save and restore register context. (It matters a lot when you have a little CPU with 4KB of program RAM.) What does it matter that it’s not pure?
- thesz 8y agoBecause if it is ot pure you will have trouble having differrent implementations of same ISA. Imagine implementing same feature for superscalar OoO or for version where pipeline length is only two or one cycle. Being a software dev I also designed CPUs. I know what I am talking about. For you having 4K IRAM - use stack machine. You'd be better off.
- deepnotderp 8y ago> ARM itself is not very nice design from contemporary point of view. I expressed my dissatisfaction with ARM ISA many times here and just let me start with two points: 1) ARM is not RISC (multiregister load/store execute in several clocks) and 2) too much of initial design of first ARM (which was not planned for longterm evolution) is visible in ISA. Found the guy who took his first computer architecture course and now thinks everyone at Intel, amd, ARM, etc is stupid for not going full on RISC.
- thesz 8y agoI think that choosing today ARM and/or Intel for your CPU of choice for product line is stupid.
- matt_the_bass 8y agoCan you list some reasons why please?
- deepnotderp 8y agoI see. Would you mind pointing me to a single competitive pure RISC CPU?
- repiret 8y ago> For example, you cannot use AMBA/APB/AXB and other ARM buses with ARM CPU core in your design without paying ARM for license for these buses Do you have a citation for that? I’m pretty sure none of the AMBA busses require a paid license to implement.
- TomVDB 8y agoThat was my understanding as well.
- thesz 8y agoTo use with ARM CPU, not to implement. When I worked with SoC design back in 2008, the situation was just like that - use A* buses freely unless you have an ARM CPU in your design (even if that CPU is implemented by you). Then you need a license. Leon family of CPUs used AXB, I think, for example.
- repiret 8y agoSo if you buy an architecture license to design your own core and you want to use AMBA in your design, you have to pay extra? I find that very surprising, but having never worked for an architecture licensee, I don’t have any information to contradict it. Can you share a sense of how expensive the bus license is relative to the architecture license?