4 ms·
To my knowledge the achievable IPC gains for a single thread are limited. Therefore it can be assumed that other players catch up in figures of IPC while the ma
by std_throwaway 8y ago
To my knowledge the achievable IPC gains for a single thread are limited. Therefore it can be assumed that other players catch up in figures of IPC while the market leader kind of gets stuck with only a tiny advantage.
- spacenick88 8y agoI keep wondering if there are some gains left by dropping the x86 legacy baggage e.g. using RISC-V or ARM64. It seems that there should be some loss due to x86 weirdness and past compromises
- std_throwaway 8y agoWhat i read was: The instruction decoder would become easier but the instruction decoder is only a small part. Most rare commands are implemented via microcode anyways, so silicon area is not hit too hard. x86 is somewhat efficient due to compact encoding compared to IA64 for example. There is surprisingly little to gain. Maybe somebody who really knows the details can chime in :)
- dgacmu 8y agoIntel usually says it's less than 3%.
- tscs37 8y agoThe peeps building Mill CPU are claiming they can do 10x performance over traditional (x86). IIRC in an early talk they explained this is mostly by bringing the IPC on a level with high IPC microcontroller arches. They do VLIW which can do a lot of things more efficiently if your compiler can handle it (Rust should be able to pull a lot of performance out of VLIW IIRC)
- gascan 8y agoVLIW plus a "sufficiently smart compiler"? Isn't that IA-64 in a nutshell?
- tscs37 8y agoBasically, though Mill also is belt-based (think stack with size-limit) not registers and compilers nowadays are a bit better at VLIW than when IA-64 was introduced. They also have a shitload of security addons that would mitigate most modern exploits and other nice-to-haves.
- deepnotderp 8y agoNah, the Mill is sufficiently different than a standard VLIW. I'm still on the fence about it, but it's noticeably different from the Itanic.