5 ms·

I wonder how much can actually be optimized due the reduced number of instructions found in risc processors. Is is the case if they need some special instructio

• rbanffy 8y ago
  Everything SIMD that relies on any flavor of SSE or AVX will need to be ported to NEON (or its variable width new thing I forgot the name). Also, many ARM SoCs have asymmetric cores - a couple i7-like ones and a couple Atom-like ones. If I see 8 cores and start 8 threads that need to sync up at the end, my process will be perceived to run at Atom speeds. At the same time, if I wake up my big powerful core to listen to me typing on a terminal, my battery will suffer - unless I have something that's "hard", I should use the small, less hungry cores. Software will need to take individual core speed in consideration when scheduling threads if it wants to achieve best possible power consumption at a certain performance level. Today, our software assumes all cores are equal. I'm not even sure these asymmetric cores have the same SIMD widths, for instance.