For people starting out, yes you can and should absolutely avoid things like Vivado if possible, because they are otherwise big, inscrutable pains in the ass, a

For people starting out, yes you can and should absolutely avoid things like Vivado if possible, because they are otherwise big, inscrutable pains in the ass, and you will hate them. Also the devices are relatively expensive comparatively. You'll be simulating a lot anyway. But, Vivado does a lot of very valuable things in practice that will take a lot of time to really replace properly, if you're doing serious FPGA work for Xilinx systems. Or even if you're doing semi-serious work. A working flow is one thing, killing it off is a much harder challenge. Even for Lattice FPGAs, IceStorm does not match e.g. Lattice iCEcube2 in terms of features or functionality (timing analysis reports, power estimation, floorplan and pinout UXs, very standard clock synthesis and constraint options, etc etc.) But it's way better at the things it actually does, admittedly. Despite that, I still find myself reaching for iCEcube2, even if my actual flow is IceStorm. These are all fixable and you can live without them, but that's for a simple EDA tool on the simplest/cheapest consumer FPGA you can buy, with a limited technology library and hard IP. The ongoing move to use tools like VPR however will polish a lot of that off (power/timing/clock constraint synthesis). XRay will benefit from that. The rest is going to be a lot of IP cores, simulation models, middleware, and software tooling, and that's what's needed to really kill off something like Vivado. Debugging tools are probably the most important middleware in particular, and they are sorely lacking. Personally at least, I will say Yosys is IMO the nicest synthesis tool there is. So, if you are OK with Verilog, the FOSS community does have some best-in-class tools already. :)