I am not sure that's necessarily true as long as the FPGA has access to the CPU bus - as it seems to here - as opposed to hanging off a slower peripheral bus -

I am not sure that's necessarily true as long as the FPGA has access to the CPU bus - as it seems to here - as opposed to hanging off a slower peripheral bus - as a lot of other FPGA experiments/cards have done in the past. If you don't penalize the FPGA with slower data access, it can make a big difference for many (albeit not all) applications.