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> The Reflections GDC demo ran on a DGX Station equipped with four Volta GPUs using NVIDIA RTX technology. For now, you will need similar horsepower to leverage

by sounds 8y ago

> The Reflections GDC demo ran on a DGX Station equipped with four Volta GPUs using NVIDIA RTX technology. For now, you will need similar horsepower to leverage real-time ray tracing. In the future, we can rely on Moore’s law to bring down the cost and complexity of how this technology is packaged and delivered. While GPUs are getting the full benefits of Dennard Scaling, much more so than Intel CPUs a la Goordon Moore, everyone is feeling the process pain of 10nm, 7nm, and beyond. It stands to reason that the major advances in real time ray tracing will be evenly split between more efficient designs and smaller transistor sizes. It seems foolish in 2018 to "rely on Moore's law" to bring a 4 x Volta GPU requirement to something more palatable for the mass market.

namibj 8y ago
Who says that we can't just drop the cost of maxing large 14nm Finfet dies and get some sort of stacking, possibly with low-tech, i.e. single-patterning, silicon interposers? The cooling/power density is not a fundamental problem, and as long as we stay under about 20-50W/cm^2 == 200-500mW/mm^2. At that heat flux we'd need 1-5mm spacing between the hot side and the other side (I do not know about experiments that cover two closely spaced hot surfaces, as you would have in slightly-spaced vertically stacked dies), and would just pump coolant with a boiling point 20K under the die's surface temperature through this. On the other side we'd get a mixture of vapor and liquid coolant, and the vapor could, at least at temperatures that a human can endure, be condensed with a small radiator and a fan, or even a larger, fanless radiator. The primary reason for such exotic packaging/stacking would be that chips need way less power to transmit over such short distances, compared to longer reach systems, as for a comparison between DDR4 and HMC [0], HMC uses about a third the power for DDR4, and that at much higher clocks. Also compare the AMD Zen IFOP intra-package links, which uses 2pJ/bit for the transceiver [1]. This should be possible to extend to an edge-mounted package (where the processor dies have contacts on one or two edges, and are soldered at a right angle to a suitable interconnection/mounting plate), though apparently no one really tried it. The downside would be that one does not have as many pins on the processor dies as currently normal, but I doubt that would be a significant problem, considering the integration benefits. A possible alternative in case of significantly improved yield would be wafer-scale integration, using the space outside of the normal reticle limit for routing larger feature-size mesh interconnects and handling the necessary routing around this later, but that would result in non-trivial software, as it would have to adapt to a given processor's routing layout. TSMC is apparently able to manufacture with reasonable yield individual 'cells' of slightly over 800mm^2, on 300mm wavers. This comes out at about 90 dies, of which some will be dead. With the power density of 50W/cm^2, that would be 3600W, but the upper limit, with significant efforts (ways to increase the flow velocity on the surface) to increase the maximum cooling capacity, would be around 100-300W/cm^2, which would put this at the TDP of an average 42U rack. The weird part would probably be some kind of reverse flip-chip packaging, where contact modules would be bonded to the functioning dies on the wafer, which would then later be fitted with some sort of cable or so, or they could be a miniature optical module. This would also need to provide the power. Cooling would be done on the back side, but the front would likely need some structural support to hold the static/dynamic pressure of the coolant without flexing/breaking. [0]: https://www.semiwiki.com/forum/attachments/content/attachments/8472d1378287921-hmc-performances.jpg https://www.semiwiki.com/forum/attachments/content/attachmen... from https://www.semiwiki.com/forum/content/2731-did-you-miss-cadence-s-memcon-q.html https://www.semiwiki.com/forum/content/2731-did-you-miss-cad... [1]: https://en.wikichip.org/wiki/amd/infinity_fabric#IFOP https://en.wikichip.org/wiki/amd/infinity_fabric#IFOP

by sounds 8y ago

namibj 8y ago

Who says that we can't just drop the cost of maxing large 14nm Finfet dies and get some sort of stacking, possibly with low-tech, i.e. single-patterning, silicon interposers? The cooling/power density is not a fundamental problem, and as long as we stay under about 20-50W/cm^2 == 200-500mW/mm^2. At that heat flux we'd need 1-5mm spacing between the hot side and the other side (I do not know about experiments that cover two closely spaced hot surfaces, as you would have in slightly-spaced vertically stacked dies), and would just pump coolant with a boiling point 20K under the die's surface temperature through this. On the other side we'd get a mixture of vapor and liquid coolant, and the vapor could, at least at temperatures that a human can endure, be condensed with a small radiator and a fan, or even a larger, fanless radiator. The primary reason for such exotic packaging/stacking would be that chips need way less power to transmit over such short distances, compared to longer reach systems, as for a comparison between DDR4 and HMC [0], HMC uses about a third the power for DDR4, and that at much higher clocks. Also compare the AMD Zen IFOP intra-package links, which uses 2pJ/bit for the transceiver [1]. This should be possible to extend to an edge-mounted package (where the processor dies have contacts on one or two edges, and are soldered at a right angle to a suitable interconnection/mounting plate), though apparently no one really tried it. The downside would be that one does not have as many pins on the processor dies as currently normal, but I doubt that would be a significant problem, considering the integration benefits. A possible alternative in case of significantly improved yield would be wafer-scale integration, using the space outside of the normal reticle limit for routing larger feature-size mesh interconnects and handling the necessary routing around this later, but that would result in non-trivial software, as it would have to adapt to a given processor's routing layout. TSMC is apparently able to manufacture with reasonable yield individual 'cells' of slightly over 800mm^2, on 300mm wavers. This comes out at about 90 dies, of which some will be dead. With the power density of 50W/cm^2, that would be 3600W, but the upper limit, with significant efforts (ways to increase the flow velocity on the surface) to increase the maximum cooling capacity, would be around 100-300W/cm^2, which would put this at the TDP of an average 42U rack. The weird part would probably be some kind of reverse flip-chip packaging, where contact modules would be bonded to the functioning dies on the wafer, which would then later be fitted with some sort of cable or so, or they could be a miniature optical module. This would also need to provide the power. Cooling would be done on the back side, but the front would likely need some structural support to hold the static/dynamic pressure of the coolant without flexing/breaking. [0]: https://www.semiwiki.com/forum/attachments/content/attachments/8472d1378287921-hmc-performances.jpg https://www.semiwiki.com/forum/attachments/content/attachmen... from https://www.semiwiki.com/forum/content/2731-did-you-miss-cadence-s-memcon-q.html https://www.semiwiki.com/forum/content/2731-did-you-miss-cad... [1]: https://en.wikichip.org/wiki/amd/infinity_fabric#IFOP https://en.wikichip.org/wiki/amd/infinity_fabric#IFOP