4 ms·
Writing HDL isn't hard but doing it right(much like with C) I would argue is the tricky part. The translation from Software -> Flip-Flops isn't nearly as natur
by vvanders 8y ago
Writing HDL isn't hard but doing it right(much like with C) I would argue is the tricky part.
The translation from Software -> Flip-Flops isn't nearly as natural and it's easy to try and apply SE techniques that while possible are totally unsuited for an FPGA.
- angry_octet 8y agoWitness the many systems that say they can translate something high level to HDL and how poorly they perform compared to an expert. It's so easy to produce logic that will run slowly or be glitchy, and most EE graduates have very limited exposure to designing logic.
- vvanders 8y agoYeah, I recall a thread earlier this week talking about a large divergence in how resets where handled between FPGAs and ASICs. It's a interesting space for sure and I'm definitely curious how these hybrid systems shake out.