3 ms·

HDLs are fine. I've found the tooling around them to be quite atrocious (slow, buggy, opaque, gui-based) though. Be it for synthesis, simulation, or even just c

• jsbto 8y ago
  Have to agree this is a major pain point for wider adoption. The current tools are mainly developed by a few big EDA vendors. I'm hoping, through the growth of open hardware communities, we'll start to see more friendly tools making progress.
• rwmj 8y ago
  Luckily there is (slow) progress on making good open source tools[1]. The Xilinx 7-series FPGAs were recently reverse-engineered too[2]. [1] https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-on-the-ice40-hx8k-fpga-breakout-board-part-1/ https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-... [2] https://github.com/SymbiFlow/prjxray https://github.com/SymbiFlow/prjxray
• craigjb 8y ago
  I’ve started using SpinalHDL, https://github.com/SpinalHDL/SpinalHDL https://github.com/SpinalHDL/SpinalHDL. It’s a Scala DSL that spits out Verilog or VHDL for traditional synthesis tools. But, unlike Chisel or MyHDL, in my opinion it’s a great experience. And, now it has seamless integration with Verilator for simulation, and the open-source Verilator project is very capable—they claim it beats commercial simulators: https://www.veripool.org/wiki/verilator https://www.veripool.org/wiki/verilator. Since Scala is quite a bit faster than Python, the simulations run much faster than something like Cocotb too! I have my hobby project in SpinalHDL up at https://craigjb.com https://craigjb.com Edit: also, GTKWave is pretty good! It’s a simple and straightforward waveform viewer that works on all platforms.
  • krupan 8y ago
    Are you writing your testbench code in C++? (that's what verilator wants, isn't it?)