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Learning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL. A former colleague is now an Altera/Intel FAE, I will ask how thi
by rjsw 8y ago
Learning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL.
A former colleague is now an Altera/Intel FAE, I will ask how things are going the next time we meet up for a beer.
- obl 8y agoHDLs are fine. I've found the tooling around them to be quite atrocious (slow, buggy, opaque, gui-based) though. Be it for synthesis, simulation, or even just compiler errors it's pretty bad compared to software.
- jsbto 8y agoHave to agree this is a major pain point for wider adoption. The current tools are mainly developed by a few big EDA vendors. I'm hoping, through the growth of open hardware communities, we'll start to see more friendly tools making progress.
- rwmj 8y agoLuckily there is (slow) progress on making good open source tools[1]. The Xilinx 7-series FPGAs were recently reverse-engineered too[2]. [1] https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-on-the-ice40-hx8k-fpga-breakout-board-part-1/ https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-... [2] https://github.com/SymbiFlow/prjxray https://github.com/SymbiFlow/prjxray
- craigjb 8y agoI’ve started using SpinalHDL, https://github.com/SpinalHDL/SpinalHDL https://github.com/SpinalHDL/SpinalHDL. It’s a Scala DSL that spits out Verilog or VHDL for traditional synthesis tools. But, unlike Chisel or MyHDL, in my opinion it’s a great experience. And, now it has seamless integration with Verilator for simulation, and the open-source Verilator project is very capable—they claim it beats commercial simulators: https://www.veripool.org/wiki/verilator https://www.veripool.org/wiki/verilator. Since Scala is quite a bit faster than Python, the simulations run much faster than something like Cocotb too! I have my hobby project in SpinalHDL up at https://craigjb.com https://craigjb.com Edit: also, GTKWave is pretty good! It’s a simple and straightforward waveform viewer that works on all platforms.
- krupan 8y agoAre you writing your testbench code in C++? (that's what verilator wants, isn't it?)
- vvanders 8y agoWriting HDL isn't hard but doing it right(much like with C) I would argue is the tricky part. The translation from Software -> Flip-Flops isn't nearly as natural and it's easy to try and apply SE techniques that while possible are totally unsuited for an FPGA.
- angry_octet 8y agoWitness the many systems that say they can translate something high level to HDL and how poorly they perform compared to an expert. It's so easy to produce logic that will run slowly or be glitchy, and most EE graduates have very limited exposure to designing logic.
- vvanders 8y agoYeah, I recall a thread earlier this week talking about a large divergence in how resets where handled between FPGAs and ASICs. It's a interesting space for sure and I'm definitely curious how these hybrid systems shake out.
- imbusy111 8y agoHow do you get into HDL and FPGAs? Seems like it will become a more and more important skill since all other avenues in performance improvement have come to a halt.
- jsbto 8y agoCould try something like Icarus Verilog for an open source compiler and start building some toy designs. There are some good communities and blogs to find help.
- rjsw 8y agoI just picked up a dev board and started making it flash LEDs, put patterns on the seven-segment display, then had a play with soft CPUs. This gave me ideas on how to use the technology in my job - embedded networking. If you are coming from a software background then maybe look at getting a board with one of the ARM+FPGA hybrid chips, you can run a proper OS on the ARM CPU and I would guess that the bus interface to the FPGA part will be simpler than using Intel's UPI.
- vvanders 8y agoI like http://www.fpga4fun.com/ http://www.fpga4fun.com/ as a decent high level overview + a bunch of great tutorials. Grab a Lattice CPLD/FPGA demo board($25-$50) and have at it!
- aseipp 8y agoLearning an HDL isn't that hard. But it's a very small part of the overall flow for real development, and arguably it's one of the easier parts anyway... That's sort of the "problem", more or less. Even very well-oiled products like the Amazon F1 and Intel's new acceleration cards are pretty non-trivial to use unless you're an experienced engineer, and they clearly spent a lot of time polishing off the roughest edges to make it as approachable as possible. Amazon more or less paid a team of seriously experienced people to make the whole flow as painless as possible (including a pretty good software SDK, and a lot of tooling around Vivado), and it's still non-trivial! Some of the ARM/FPGA combos are a lot more approachable overall, but the tooling, BSPs etc are normally huge pains the moment you want to get creative, and the SDKs are comparatively worse, vs the "high end" ones listed above, in my opinion. Normally I just end up replacing them with my own Linux BSP, more or less, if I need the actual host side. A really annoying aspect of all this though is that most kits which could offer features like high-speed peripherials (PCIe, etc) are pretty expensive for hobbyist developers to acquire and use, so there's certainly a bit of a self-fulfilling-prophecy going on here.
- rjsw 8y agoI have an ARM+FPGA system (Xilinx Zynq), I don't use the supplied BSP either.
- kevin_thibedeau 8y agoThere are a multitude of foot bullets that you can generate when synthesizing valid HDL to real world hardware. These languages were meant for specification and simulation and as such allow you to do things that are plainly wrong for synthesis in the real world. It's very easy to generate a circuit that works 99.9% of the time and causes Heisenbugs if you approach it like software programming.