They never acknowledged Gary, but removed him anyway. The original said "Scalar floating-point instructions operate on single 32-bit operands that reside in th

They never acknowledged Gary, but removed him anyway. The original said "Scalar floating-point instructions operate on single 32-bit operands that reside in the lower 32-bits of the GPRs. These instructions are considered a proper subset of the SPE APU; this subset is referred to as the SPFPU now called the EFPU Gary cares only that it have embedded in it somewhere." (more recent e500 chips considered the scalar instructions to be in a separate APU)