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It’s about time Intel offers consumers ECC RAM support.

• snvzz 8y ago
  While it won't necessarily help you with this, AMD has support in all Zen CPUs, not just the EPYC server series.
• deleted 8y ago
  [deleted]
• rasz 8y ago
  ECC wont help, you need row access counters(target row refresh/TRR) directly in ram chips, or in memory controller. With switch to DDR4 JEDEC had a chance of standardizing those mitigations, but that would cost additional cents per chip, cant have that!
  • justin66 8y ago
    Do you have any links to more information on that? Googling "row access counters" leads to a lot of comments you've made on the internet, and nothing else. I'm skeptical that "ECC won't help," that's not a commonly held opinion. It might be true but it'd be interesting to read some actual analysis as to why.
    • Ajedi32 8y ago
      ECC may indeed help, but it wouldn't really fix the root of the problem: the fact that bit flips like this can happen at all.
    • jnwatson 8y ago
      From the original paper, "For example, SECDED (single error-correction, double error detection) can correct only a single-bit error within a 64-bit word. If a word contains two victims, however, SECDED cannot correct the resulting double-bit error. And for three or more victims, SECDED cannot even detect the multi-bit error,leading to silent data corruption. Therefore, we conclude that SECDED is not failsafe against disturbance errors." The challenge for the attacker is to produce a 3 or more bit failure before a 2-bit failure occurs, which would trigger some alarms. I haven't seen any research on the feasibility of such an attack. Additionally, there are stronger ECC schemes than SECDED, for example the one in IBM's ChipKill. It is hard to imagine a RowHammer attack that could remain undetected with such a scheme. It is fair to say that ECC memory raises the bar for attackers.
      • nickpsecurity 8y ago
        Not to mention the schemes that treat RAM as untrusted with cryptographic, integrity checks. Those architectures are making more sense than ever now.
    • rasz 8y ago
      google target row refresh, TRR
  • toast0 8y ago
    ECC doesn't solve rowhammer, but it raises the difficulty. If you only get a single bit error, ECC will fix it, and increase a counter / raise a usually slow interrupt, if you get a lot of them, perf will be impacted, and the operator should notice. If you get a double bit error, ECC will (generally) halt the os, and the operator will definitely notice. -- you won't get to try very much. If you get a multi bit error, maybe you can do your nefarious task.
  • als0 8y ago
    And TRR itself is not sufficient. From the paper "The idea of TRR is to refresh adjacent rows if the targeted row is accessed at a high frequency. More specifically, TRR works with a maximum number of activations allowed during one refresh cycle, the maximum active count. Thus, if a double-sided Rowhammer attack (Section 2.2) is mounted, and two hammered rows are accessed more than the defined maximum active count, the adjacent rows (in particular the victim row of the attack) will be refreshed. As the potential victim rows are refreshed, in theory, no bit flip will occur, and the attack is mitigated. However, in practice, bit flips can be further away from the hammered rows and thus TRR may be ineffective"
    • rasz 8y ago
      I read that paper. Next iteration or TRR could have cascaded adders with dividers for X neighbor rows. But first we need JEDEC to grab current industry players by the throat and force their colluding asses to at least start doing something by adopting TRR in desktop/server products :(