3 ms·
I think ARM's "strongly-ordered memory" concept is supposed to solve this? Was your friend's problem intended behavior, or a silicon bug? http://infocenter.arm
by tripletao 8y ago
I think ARM's "strongly-ordered memory" concept is supposed to solve this? Was your friend's problem intended behavior, or a silicon bug?
http://infocenter.arm.com/help/topic/com.arm.doc.dai0321a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf http://infocenter.arm.com/help/topic/com.arm.doc.dai0321a/DA...
- Gibbon1 8y agoI think the DMA accesses were confusing the memory controller. He said that sort of thing was common on internally developed silicon. They won't do a spin if there is a work around. Also my experience as well. I've had to deal with peripherals with an async clock where access timing becomes important. Observation: CS appears to teach students that code with side effects is evil. AKA hide you side effects behind os calls. With embedded code side effects are important.