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You can not express the needed instructions in standard C or C++ code. Some compilers may have intrinsics. The inline assembly for gcc on PowerPC might be: __a
by burfog 8y ago
You can not express the needed instructions in standard C or C++ code. Some compilers may have intrinsics. The inline assembly for gcc on PowerPC might be:
__asm__ __volatile__("eieio":::"memory");
Normally the CPU will freely reorder loads and stores that go to different addresses. It is not necessarily reordering instructions; the reordering happens on the way to the memory bus.
That special instruction helps. It will ensure that previous accesses to IO memory will be done before any that follow. It also has a similar effect in RAM, but sadly not between RAM and IO memory. For that, which might be needed for a DMA engine, you'll also need the "sync" instruction.
- viraptor 8y agoSorry, autocorrect, can't fix it anymore. I wanted to write exposed, not expressed. And yes, either via inline ASM or intrinsics.
- BenFrantzDale 8y ago“You can not express the needed instructions in standard C or C++ code.“ As of 2011, you can. In C++ it’s with std::atomic. http://en.cppreference.com/w/cpp/atomic/atomic http://en.cppreference.com/w/cpp/atomic/atomic C11 offers comparable tools, I believe.
- burfog 8y agoNo, that is only good enough for threads. The compiler is not required to insert special instructions like "eieio" and is even free to optimize things in ways that would cause misbehavior of hardware. For example, consider two values written to the same location. The compiler is free to optimize out the first one because no valid threaded program can depend upon seeing that value briefly appear.
- BenFrantzDale 8y agoIf I understand you and the standard correctly, no: the default behavior is `memory_order_seq_cst` "On weakly-ordered systems (ARM, Itanium, PowerPC), special CPU load or memory fence instructions have to be used." http://en.cppreference.com/w/cpp/atomic/memory_order http://en.cppreference.com/w/cpp/atomic/memory_order I'm not 100% sure what you mean by your second paragraph. I think you are saying that repeated writes to a `std::atomic` can be optimized out, which sounds like it is true since `std::atomic` is not `volatile`. https://stackoverflow.com/questions/45960387/why-dont-compilers-merge-redundant-stdatomic-writes https://stackoverflow.com/questions/45960387/why-dont-compil...