Wouldn't agree they're both buggy, assuming the aliasing isn't an issue given the upstream types. The author mentions the potential of hardware re-ordering in T

Wouldn't agree they're both buggy, assuming the aliasing isn't an issue given the upstream types. The author mentions the potential of hardware re-ordering in TFA. C++11 atomics are suggested though not sure that'd deal with the issue unless the compilers utilize a bulk memory copy operation. The proposed alternative of using a struct appears more confusing at first, but it's really helpful when referring back to the register layouts. TI makes pretty good usage of the method for the co-processors in the BeagleBones [1]. Generally I think it's nicer to have a `settings->control_bit = 1` than `*(base_prt + control_bit_offset) = 1`. Though the whole `reinterpret_cast` and volatile stuff in C++ confuses me everytime. C is _much_ easier but less type safe when dealing with volatile. 1: http://processors.wiki.ti.com/index.php/PRU-ICSS_Header_Files http://processors.wiki.ti.com/index.php/PRU-ICSS_Header_File...