I agree with you: it pays to be skeptical of these high level design flows. I'm wary of HLS even from established vendors. However, if it targets FPGA, and not

I agree with you: it pays to be skeptical of these high level design flows. I'm wary of HLS even from established vendors. However, if it targets FPGA, and not ASICs, maybe the reset omission is on purpose. FPGA guarantees initialization on load and the some registers may not need to be cleared after usage. On the other hand, a reset signal consumes precious routing resources spanning large areas. But I surely would triple-check this, even for FPGA use. I expect to actually do so in a few weeks. EDIT: Ok, this comment sit far too long in the edit box before posting. Now I see the huge discussion in this thread. I'll keep this comment anyway.