It's not old school, it's standard practice in the ASIC design industry. You mentioned those papers but you didn't link them, so I will have to guess that this

It's not old school, it's standard practice in the ASIC design industry. You mentioned those papers but you didn't link them, so I will have to guess that this is the one in order to address your comment: - https://www.xilinx.com/support/documentation/white_papers/wp272.pdf https://www.xilinx.com/support/documentation/white_papers/wp... I guess the keyword here is "FPGA design". The author of the paper argues that the FPGA already offers an abstraction layer that allows the designer to ignore the problem for certain occasions in order to save up on area. > The good news is that 99.99% of the time, the timing of the reset release really doesn't matter. (...) However, if you have ever had one of the circuits that doesn’t work the first time, then maybe you have encountered one of the 0.01% cases and have been unlucky enough to have released the reset at the wrong time. > A design implemented in a Xilinx FPGA does not require insertion of a global reset network. For the vast majority of any design, the initialization state of all flip-flops and RAM following configuration is more comprehensive than any logical reset will ever be. There is no requirement to insert a reset for simulation because nothing will be undefined. But it doesn't mean it is 100% correct as this design would be very poor if it was ever translated to an ASIC. I guess since this project is done with FPGA design in mind, the strict ASIC design rules don't apply here.