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Very interesting that this doesn't seem to lean on any existing compiler toolchains - it all appears hand written from compiler through cpu generation. I wonde
by ris 8y ago
Very interesting that this doesn't seem to lean on any existing compiler toolchains - it all appears hand written from compiler through cpu generation.
I wonder how the results compare to something like TCE http://tce.cs.tut.fi/ http://tce.cs.tut.fi/ which takes advantage of the LLVM ecosystem.
Given the lack even of advanced c-compiler optimizations and the inherent drawbacks of FPGAs, can this even beat the power or speed performance of a software implementation running on e.g. a modern ARM core?
- TomVDB 8y agoI wish the documentation gave more details about the whole conversion process. I'm guessing that the RISC core gets optimized by dropping instructions that aren't needed for a particular C program. But does it have some kind of heuristic to determine whether or not to drop an instructions based on how often it's used? Or is it just a greedy "If the C compiler generates instruction A, then add instruction A to the CPU" decision?