4 ms·
On this particular thing I think the Intel docs are clear. This is where I implemented the same in JPC: https://github.com/ianopolous/JPC/blob/master/src/org/j
by ianopolous 8y ago
On this particular thing I think the Intel docs are clear. This is where I implemented the same in JPC:
https://github.com/ianopolous/JPC/blob/master/src/org/jpc/emulator/execution/decoder/Disassembler.java#L351 https://github.com/ianopolous/JPC/blob/master/src/org/jpc/em...
- an_account_name 8y agoThey might be clear today. Were they always? There are literally decades of timeline to examine here.
- ianopolous 8y agoThey were clear in 2006 when I was reading them. All the emulator implementors were very aware of it. Many old operating systems won't boot without the delay.
- caf 8y agoThe interrupt shadow itself is clear. The specific implication of that for a mov ss ; syscall pair with a hardware breakpoint set on the first instruction is a lot more subtle.
- ianopolous 8y agoAgreed, but that's just saying that combining two or more simple things results in a more complex thing. All platforms I know of describe each individual instruction and its consequences, and leave you to deduce the consequences of combining them.