3 ms·

> Old chips are rated for 10k erases. Newer is 100k+. Isn't this backwards? I was under the impression that as NAND moved to store more bits per cell (SLC -> M

• userbinator 9y ago
  Yes, endurance and retention decreases exponentially with increasing bits per cell and is correlated with the capacity process size too --- higher density NAND made on a smaller process obviously has less area to store a charge in the first place, and the smaller gate oxide means less endurance. In the "good old days" SLC was typically 100K cycles and MLC 10K, now even good SLC is around 10K with MLC at 5K, and the newest TLC is ~1K or less. Manufacturers are, not surprisingly, increasingly secretive about the decreasing reliability of their products. It's only with complex error correction that such chips can even be used at all.