5 ms·

Seems really useful, but if my knowledge of flash memory is accurate, this testing process could highly degrade the memory you run it on. Due to quantum tunneli

Seems really useful, but if my knowledge of flash memory is accurate, this testing process could highly degrade the memory you run it on. Due to quantum tunneling, erasures are very hard on flash memory, often the limiting endurance factor. That is one method mentioned for testing the chip in the article. Writing all 1's then erasing to all 0's multiple times to see what percentage are correct. On an already dated device this could be catastrophic!

kevin_thibedeau 8y ago
A few dozen erases for testing are inconsequential. They are meant to be used. Old chips are rated for 10k erases. Newer is 100k+. Only the most ancient parts have lower wear limits and nobody designs them into new products. The 10k parts are all going EOL now.
- ac29 8y ago
  > Old chips are rated for 10k erases. Newer is 100k+. Isn't this backwards? I was under the impression that as NAND moved to store more bits per cell (SLC -> MLC -> TLC), endurance went down, not up.
  - userbinator 8y ago
    Yes, endurance and retention decreases exponentially with increasing bits per cell and is correlated with the capacity process size too --- higher density NAND made on a smaller process obviously has less area to store a charge in the first place, and the smaller gate oxide means less endurance. In the "good old days" SLC was typically 100K cycles and MLC 10K, now even good SLC is around 10K with MLC at 5K, and the newest TLC is ~1K or less. Manufacturers are, not surprisingly, increasingly secretive about the decreasing reliability of their products. It's only with complex error correction that such chips can even be used at all.
628C6l0 8y ago
Until I saw 'chip', I thought this is about flashbulb memory (https://en.wikipedia.org/wiki/Flashbulb_memory https://en.wikipedia.org/wiki/Flashbulb_memory) and made a mental note to myself not to 'take' the test under any circumstances.
neolefty 8y ago
I doubt they're writing the whole chip—instead, a statistical sampling seems sufficient. And wouldn't most controllers already handle accumulating errors, including any introduced by the testing process? I understood that a portion of flash storage is set aside for redundancy.
- Arbalest 8y ago
  I don't think that is a safe assumption. While good controllers do wear levelling, there are many that have less capable wear levelling. Also, even with reserve blocks, having a constantly full drive can make inferior controllers cause abnormal wear. This is probably less of a problem even with lower end controllers today, but let's not forget the early Sandforce controllers... those chips could be part of the recycling process.

kevin_thibedeau 8y ago

A few dozen erases for testing are inconsequential. They are meant to be used. Old chips are rated for 10k erases. Newer is 100k+. Only the most ancient parts have lower wear limits and nobody designs them into new products. The 10k parts are all going EOL now.

ac29 8y ago
> Old chips are rated for 10k erases. Newer is 100k+. Isn't this backwards? I was under the impression that as NAND moved to store more bits per cell (SLC -> MLC -> TLC), endurance went down, not up.
- userbinator 8y ago
  Yes, endurance and retention decreases exponentially with increasing bits per cell and is correlated with the capacity process size too --- higher density NAND made on a smaller process obviously has less area to store a charge in the first place, and the smaller gate oxide means less endurance. In the "good old days" SLC was typically 100K cycles and MLC 10K, now even good SLC is around 10K with MLC at 5K, and the newest TLC is ~1K or less. Manufacturers are, not surprisingly, increasingly secretive about the decreasing reliability of their products. It's only with complex error correction that such chips can even be used at all.

628C6l0 8y ago

Until I saw 'chip', I thought this is about flashbulb memory (https://en.wikipedia.org/wiki/Flashbulb_memory https://en.wikipedia.org/wiki/Flashbulb_memory) and made a mental note to myself not to 'take' the test under any circumstances.

neolefty 8y ago

I doubt they're writing the whole chip—instead, a statistical sampling seems sufficient. And wouldn't most controllers already handle accumulating errors, including any introduced by the testing process? I understood that a portion of flash storage is set aside for redundancy.

Arbalest 8y ago
I don't think that is a safe assumption. While good controllers do wear levelling, there are many that have less capable wear levelling. Also, even with reserve blocks, having a constantly full drive can make inferior controllers cause abnormal wear. This is probably less of a problem even with lower end controllers today, but let's not forget the early Sandforce controllers... those chips could be part of the recycling process.